The design of integrated circuits (ICs) is increasing in complexity on a regular basis. Timing and power requirements in the final implementation are very critical and require adherence to complex timing constraints to ensure proper implementation and realistic timing analysis. More and more transistors are integrated on a single semiconductor device in ever increasing complexity of functions and modules. As design and manufacturing costs of such ICs have also become significant, it is essential to verify that the design and corresponding constraints have no flaws (also referred to as bugs) and may be at least substantially, if not completely, operative from the first manufacturing cycle. Typically, designers rely on manual review of design constraints including timing exceptions such as setting a path as a false-path or a multi-cycle path, typically done in the likes of Synopsis design constraint (SDC). This manual review is prone to human errors, especially as the design and corresponding constraints complexity increases in order to meet functionality, speed and power requirements of today's complex ICs.
An advance in the art over manual review of design constraints, known as static formal verification of timing exceptions, has been proposed in an attempt to automate the manual review process. This approach, purely functional, ignores the timing nature of exceptions leading to a very high number of false errors that take both time and effort to review and dispose of as false errors. For example, designers define timing exceptions on signals that are not expected to toggle during the functional execution of the design. This type of exceptions will be proved as false exceptions by a formal verification tool ignoring the static nature of the signal. Such false errors will require a manual review in order to dispose them of as false errors and keep the exceptions defined as correct exceptions. Due to close to 100% false-violations, an effect also known as ‘tool noise’, designers have not generally adopted this automated exception verification approach.
In view of the deficiencies of the prior art it would be advantageous to provide a solution for IC design constraints verification that is able to overcome the deficiencies of the prior art.